1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a dynamic random access memory (RAM) device comprising one-transistor, one-capacitor-type memory cells.
2. Description of the Prior Art
In a MOS dynamic RAM device, one-transistor, one-capacitor-type memory cells have been put to practical use, and, in addition, such memory cells are often used since they are advantageous in respect to integration density. In this type of memory cell, each cell comprises a capacitor and a transistor which serves as a switching element for charging and discharging the capacitor. Therefore, the presence or absence of charges in the capacitor represents data "1" or "0", respectively. The memory cells are arranged at intersections between word lines and bit lines. In addition, dummy cells are arranged at intersections between dummy word lines and bit lines.
In the prior art, these dummy cells are similar in construction to the one-transistor, one-capacitor-type memory cells in that they comprise a capacitor, a transistor, and an additional transistor for resetting the capacitor. However, in recent years, dummy cells comprising only one capacitor have been developed (See: IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 184-189, April 1980). A dynamic RAM including such one-capacitor dummy cells is advantageous in respect to integration density and reduces the load of the operation clock generator.
In a dynamic RAM device including the above-mentioned one-capacitor-type dummy cells, a discharging transistor and a charging transistor are provided in series between two power supplies (V.sub.CC, V.sub.SS), and their connection node is connected to a dummy word line connected to the dummy cells. The control of this device is carried out as follows. First, the dummy word line is discharged by the discharging transistor clocked by a reset clock generator. In this state, the dummy word line is at level V.sub.SS. Then, the dummy word line is charged by the charging transistor clocked by an operation clock generator so that the potential of the dummy word line is pushed up to the power supply voltage (V.sub.CC).
In the above-mentioned dynamic RAM device, however, in order to push up the potential of the dummy word line, the operation clock generator must generate a potential higher than V.sub.CC +V.sub.th, where V.sub.th is the threshold voltage value of the charging transistor. As a result, the operation clock generator has to incorporate a charge-pumping circuit or a bootstrap circuit for generating such a higher potential. Therefore, the operation clock generator becomes complex, and, accordingly, the operation speed of the operation clock generator, that is, the access speed of the device, becomes low.